Understanding PCIe Physical Layer

The PCIe Physical Layer is responsible for converting structured packet data into high-speed electrical signals that can traverse the link between devices. While higher layers define what to send, the Physical Layer determines how those bits are transmitted reliably over a noisy channel. This article focuses on the transmit (TX) path, breaking down each stage from TLP data to differential signaling on the wire, including scrambling, encoding, and serialization. PCIe Physical Layer The Root Complex (RC) and Endpoint (EP) are connected by a PCIe Link — a set of high-speed differential signal pairs. Everything that happens between them (register reads, DMA transfers, interrupts) is ultimately carried as Transaction Layer Packets (TLPs) over this link. +-------------+ +-------------+ | |<====== PCIe Link ========> | | | RC | | EP | | | | | +-------------+ +-------------+ PCIe Link A PCIe lane is a full-duplex serial connection consisting of one transmit pair and one receive pair. A PCIe li