Inside PCIe PHY: End-to-End Transmit and Receive Path

This article builds on the PCIe overview and physical layer fundamentals by presenting an end-to-end view of how data flows through the transmit and receive paths. The focus is on how a Transaction Layer Packet (TLP) is transformed into a high-speed serial bit stream and reconstructed at the receiver. ============================================================================ TRANSMITTER (e.g., Root Complex sending a Memory Write TLP) ============================================================================ [Data Link Layer] Seq# + TLP Header + Data + LCRC (parallel bytes) | v [Physical Layer] [Framing / Block Formation] Gen1/2: STP + TLP + END (control symbols embedded in stream) Gen3+: Data organized into 128-bit blocks (packet boundaries inferred, no explicit STP/END) | v [Scrambler] Bit stream XOR’d with LFSR sequence -> Randomized data for transition density and EMI reduction | v [Encoder / Block Encoding] Gen1/2 (8b/10b): 8-bit -> 10-bit symbol (DC balance + control encoding)