HBM4 Didn't Break the Memory Wall — It Just Moved It

HBM4 Didn't Break the Memory Wall — It Just Moved It HBM bandwidth has doubled every generation. HBM2E (2020): 410 GB/s per stack — 1024-bit, 3.2 Gb/s/pin HBM3 (2022): 819 GB/s per stack — 1024-bit, 6.4 Gb/s/pin HBM3E (2024): 1.2 TB/s per stack — 1024-bit, up to 9.8 Gb/s/pin (JEDEC max, varies by vendor) HBM4 (2026): 2.0 TB/s per stack — 2048-bit, 8.0 Gb/s/pin Notice anything off? HBM4's JEDEC base pin speed is 8.0 Gb/s. That's lower than HBM3E's max JEDEC spec of 9.8 Gb/s (Samsung's implementation; SK Hynix HBM3E runs at 8 Gb/s). Bandwidth doubled, but the base spec pin speed didn't go up. The majority of the bandwidth gain comes from doubling the interface width (1024 to 2048 bits). They didn't make the pipe faster. They made it wider. That was HBM4's design decision, and it was driven by physics hitting back. Why Pin Speed Hit a Ceiling The Signal Integrity Wall # HBM per-pin speed progression pin_speed_history = { " HBM2E " : { " speed " : 3.2 , " unit " : " Gb/s " , " year " : 202